1. Field of the Invention
This invention relates to a substrate for mounting of a semiconductor chip, and to a method for manufacturing a semiconductor device.
2. Description of the Related Art
A substrate for mounting of a semiconductor chip (mounting substrate) generally has a plurality of mounting regions as shown in FIG. 6(A). A semiconductor device is conventionally mounted as described below.
Semiconductor chips 52 are mounted on mounting regions 60a-60d of a mounting substrate 50, respectively. Pads 54 of each semiconductor chip are connected by bonding wires to inner electrodes 56 of a corresponding mounting region. The mounting regions 60a-60d are then filled with resin, and the mounting substrate 50 is diced into individual semiconductor devices.
As seen in FIG. 6(B), inner electrodes 56a and 56b are formed on the mounting substrate 50, and each inner electrode 56a, 56b is connected to an outer electrode via through holes (not shown). These inner electrodes 56 are generally formed by electroplating. All of the inner electrodes 56 are electrically and physically connected to each other by interconnections 58 and 59 before the mounting substrate 50 is diced along dicing line 62 into individual semiconductor devices. However, after dicing, the inner electrodes 56 should be electrically isolated from one another.
The interconnect wiring pattern 58 corresponds to the dicing line, and the interconnect wiring pattern 58 is supposed to be removed by a dicing blade during dicing the mounting substrate. However, if the position of the dicing blade is shifted, a portion of the interconnect wiring pattern 58 remains as shown in FIG. 6(C). In some cases, the remaining portion of the interconnect wiring pattern 58 connects one inner electrode to another inner electrode, thus short-circuiting the inner electrodes.
An object of the present invention is to solve the above-described problem.
According to one aspect of this invention, for achieving the above object, A mounting substrate includes a substrate body having at least first and second adjacent chip mounting regions defined on a surface thereof, and further having a dicing line defined between the first and second mounting regions; a first plurality of inner electrodes aligned along a first side of the first chip mounting region, a second plurality of inner electrodes aligned along a second side of the second chip mounting region, wherein the first side of the first chip mounting region confronts the second side of the second chip mounting region, an interconnect wiring pattern located between the first and second chip mounting region, and commonly connected to the first plurality of inner electrodes and the second plurality of inner electrodes, wherein the interconnect wiring pattern includes a plurality of connected wiring portions, and wherein at least some of said wiring pattern extend obliquely across the dicing line.